A link register (LR for short) is a register which holds the address to return to when a subroutine call completes. This is more efficient than the more traditional scheme of storing return addresses on a call stack, sometimes called a machine stack. The link register does not require the writes and reads of the memory containing the stack which can save a considerable percentage of execution time with repeated calls of small subroutines.
The IBM POWER architecture, and its PowerPC and Power ISA successors, have a special-purpose link register, into which subroutine call instructions put the return address. In some other instruction sets, such as the ARM architectures, SPARC, and OpenRISC, subroutine call instructions put the return address into a specific general-purpose register, so that register is designated by the instruction set architecture as the link register. In some others, such as PA-RISC, RISC-V, and the IBM System/360 and its successors, including z/Architecture, the subroutine call instruction can store the return address in any general-purpose register; a particular register is usually chosen, by convention, to be used as the link register.
The ARMv7 architecture uses general-purpose register R14 as the link register,[1][2] OpenRISC uses register r9,[3] and SPARC uses "output register 7" or o7.[4]
Some architectures have two link registers: a standard "branch link register" for most subroutine calls, and a special "interrupt link register" for interrupts. One of these is ARCv2 (ARC processors using version 2 of the ARCompact architecture), which uses general-purpose-registers r29 for the interrupt link register and r31 for the branch link register.[5][6] References to "the link register" on such platforms will be referring to the branch link register.
Earlier ARC processors based on the ARCompact and ARCtangent architectures had three link registers: two interrupt link registers (ILINK) and one branch link register (BLINK).[5][7][8][9] The two interrupt link registers were ILINK1 (for level 1 (low priority) maskable interrupts), and ILINK2 (for level 2 (mid priority) maskable interrupts). In these architectures, r29 was used as the level 1 interrupt link register, r30 as the level 2 interrupt link register, and r31 as the branch link register. ILINK1 and ILINK2 were not accessible in user mode on the ARC 700 processors.[7]
The use of a link register, regardless of whether it is a
dedicated register or a general-purpose register, allows for faster
calls to leaf subroutines.
When the subroutine is non-leaf, passing the return address in a
register can still result in generation of more efficient code for thunks,
e.g. for a subroutine whose sole purpose is to call another subroutine
with arguments rearranged in some way. Other subroutines can benefit
from the use of the link register because it can be saved in a batch
with other callee-used registers—e.g. an ARM subroutine pushes registers
4-7 along with the link register, LR, by the single instruction
STMDB SP!, {R4-R7, LR} pipelining all memory writes required.
References
- "Lauterbach". Archived from the original on 1 May 2016. Retrieved 25 August 2022.
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https://en.wikipedia.org/wiki/Link_register
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