In computing, traditionally cycle stealing is a method of accessing computer memory (RAM) or bus without interfering with the CPU. It is similar to direct memory access (DMA) for allowing I/O controllers to read or write RAM without CPU intervention. Clever exploitation of specific CPU or bus timings can permit the CPU to run at full speed without any delay if external devices access memory not actively participating in the CPU's current activity and complete the operations before any possible CPU conflict.
Cycle stealing was common in older platforms, first on supercomputers which used complex systems to time their memory access, and later on early microcomputers where cycle stealing was used both for peripherals as well as display drivers. It is more difficult to implement in modern platforms because there are often several layers of memory running at different speeds, and access is often mediated by the memory management unit. In the cases where the functionality is needed, modern systems often use dual-port RAM which allows access by two systems, but this tends to be expensive.
In older references, the term is also used to describe traditional DMA systems where the CPU stops during memory transfers. In this case the device is stealing cycles from the CPU, so it is the opposite sense of the more modern usage.
In the smaller models of the IBM System/360 and System/370, the control store contains microcode for both the processor architecture and the channel architecture. When a channel needs service, the hardware steals cycles from the CPU microcode in order to run the channel microcode.
https://en.wikipedia.org/wiki/Cycle_stealing
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